1. Field of the Invention
This invention is related to the field of processors and, more particularly, to reference and change bit updates to page table entries in processors.
2. Description of the Related Art
Processors typically implement address translation. When address translation is enabled, fetch addresses and load/store addresses are effective or virtual addresses. The effective/virtual address is translated through the address translation mechanism to arrive at a physical address (or real address). The terms physical address and real address, as used herein, are intended to be synonymous. The physical/real address is the address actually used to address memory. For example, the PowerPC™ instruction set architecture defines an effective address that is translated through a segment mechanism to a virtual address, and the virtual address is translated through a page table to a physical/real address. An effective address is the address generated to fetch the instruction (also referred to as the program counter, or PC, of the instruction) or the address generated from the address operands of a load/store instruction. The PC is often generated by adding an offset to the current PC depending on whether a sequential or branch target fetch is being generated. In some cases, the effective address is equal to the virtual address. In other cases, the virtual address is generated based on the effective address (e.g. translated from the effective address, or generated by applying some predetermined operation on the effective address).
Address translation is used for a variety of reasons. For example, address translation can be used to provide a larger effective or virtual address space than the amount of physical memory included in the computer system could support. A slower secondary storage (e.g. disk storage) can be used as a page swap storage to swap pages in and out of the memory as needed by the program(s) being executed. Additionally, address translation can be used in multitasking environments to protect one tasks memory from access/update by another task, and to provide each task with its own address space independent of which physical pages are allocated to the task. If the overall memory usage of the tasks exceeds the memory size, page swapping can again be used to retain memory contents and provide access to the pages that are currently in use.
Page tables, which store the virtual to physical translation mappings, may include information to aid in the page swapping process. For example, reference bits and change bits are commonly included in the page table entries. The reference bit is set in a corresponding page table entry by the processor hardware when the page is referenced (e.g. either read or written). The change bit is set in the corresponding page table entry by the processor hardware if data in the page has been modified (e.g. via execution of a store instruction). The page management software may use the reference and change bits to determine which pages to page out to secondary storage. For example, the page management software may periodically clear the reference bits and may use the reference bits as an indicator of recent access. When a page is selected to be paged out, a page with the reference bit clear may be a good choice. If no pages have the reference bit clear, a page which has been referenced but not modified (change bit clear) may be a good choice since the page may not necessarily be written to the disk, since it can be read from its original source again when needed. If the change bit is set, the page may be paged out to disk and the changes retained.
Accordingly, the processor hardware generates updates to the page table entries. When software is modifying the page tables, or otherwise needs to ensure that pending page table entry updates have completed, software may use a predefined synchronization instruction that is defined to ensure that pending page table entry updates are complete. In multiprocessing environments, a synchronization operation is transmitted to each processor over the interconnect between the processors. Each processor ensures that its pending page table entry updates are completed before permitting the synchronization operation to complete. For example, in some cases, the processors retry the synchronization operation until the processors have completed the pending page table entry updates.
Typically, each processor in the system freezes the generation of page table entry updates and completes the pending page table entry updates. All processors then await the completion of the synchronization operation before unfreezing. Such a process correctly completes the pending page table entry updates, but also causes the processors to wait in the frozen state for a long period of time, in some cases.